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Publications

CAESAR

E. Homsirikamol and K. Gaj, "Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study," in 2017 International Conference on Field Programmable Technology - FPT 2017, Melbourne, Australia, Dec. 2017. (slides + accepted version)

W. Diehl, A. Abdulgadir, J.-P. Kaps and K. Gaj, "Comparing the Cost of Protecting Selected Lightweight Block Ciphers Against Differential Power Analysis in Low-Cost FPGAs," in 2017 International Conference on Field Programmable Technology - FPT 2017, Melbourne, Australia, Dec. 11-13, 2017. (slides + accepted version)

F. Farahmand, A. Ferozpuri, W. Diehl and K. Gaj, "Minerva: Automated Hardware Optimization Tool," in 2017 International Conference on Reconfigurable Computing and FPGAs - ReConFig 2017, Cancun, Mexico, Dec. 4-6, 2017. (poster + accepted version)

S. Deshpande and K. Gaj, "Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates," 19th Euromicro Conference on Digital System Design - DSD 2017, Vienna, Austria, Aug. 30-Sep. 1, 2017. (slides + accepted version)

W. Diehl and K. Gaj, "RTL Implementations and FPGA Benchmarking of Selected CAESAR Round Two Authenticated Ciphers," Microprocessors and Microsystems, vol. 52, July 2017, pp. 202-218.

E. Homsirikamol and K. Gaj, "AEZ: Anything-but EaZy in Hardware," 17th International Conference on Cryptology in India - Indocrypt 2016, Kolkata, India, Dec. 11-14, 2016. (slides + accepted version)

W. Diehl and K. Gaj, "RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two," 19th Euromicro Conference on Digital Systems Design, DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016. (slides + accepted version)

W. Diehl and K. Gaj, "Implementation of a Boolean Masking Scheme for the SCREAM Cipher," 19th Euromicro Conference on Digital System Design - DSD 2016, Limassol, Cyprus, Aug. 31-Sep. 2, 2016. (poster + accepted version)

E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, P. Yalla, J.-P. Kaps and K. Gaj, "CAESAR Hardware API," Cryptology ePrint Archive: Report 2016/626, June 2016. (report)

E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, "A Universal Hardware API for Authenticated Ciphers," 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, Mayan Riviera, Mexico, Dec. 7-9, 2015. (slides + accepted version)

P. Morawiecki, K. Gaj, E. Homsirikamol, K. Matusiewicz, J. Pieprzyk, M. Rogawski, M. Srebrny, and M. Wójcik, "ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption," in LNCS 8731, Cryptographic Hardware and Embedded Systems - CHES 2014, Busan, South Korea, Sep. 23-26, 2014. (slides + ePrint version)

SHA-3

F. Farahmand, E. Homsirikamol, and K. Gaj, "A Zynq-based Testbed for the Experimental Benchmarking of Algorithms Competing in Cryptographic Contests," 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, Nov. 30-Dec. 2, 2016. (poster + accepted version)

E. Homsirikamol and K. Gaj, "Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study," in LNCS 9040, 11th International Symposium on Applied Reconfigurable Computing, ARC 2015, Bochum, Apr. 13-17, 2015, pp. 217-228. (accepted version)

P. Yalla, E. Homsirikamol, and J.-P. Kaps, "Comparison of Multi-purpose Cores of Keccak and AES," Design, Automation Test in Europe, DATE 2015, ACM, Mar. 2015, pp. 585-588. (short talk + poster + accepted version)

K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, "Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs," Cryptology ePrint Archive: Report 2012/368, first version - June 2012, final version - October 2012. (report)

M. Rogawski and K. Gaj, "Groestl Tweaks and Their Effect on FPGA Results," Cryptology ePrint Archive: Report 2011/635, Nov. 2011. (report)

R. Shahid, U. Sharif, M. Rogawski, and K. Gaj, "Use of Embedded FPGA Resources in Implementations of 14 Round 2 SHA-3 Candidates," in 2011 International Conference on Field Programmable Technology - FPT 2011, New Delhi, India, Dec. 2011. (slides + accepted version)

J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, "Lightweight implementations of SHA-3 candidates on FPGAs," in LNCS 7107, Progress in Cryptology - INDOCRYPT 2011, Dec. 2011, pp. 270-289. (slides + accepted version)

E. Homsirikamol, M. Rogawski, and K. Gaj, "Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs," in LNCS 6917, Cryptographic Hardware and Embedded Systems - CHES 2011, Nara, Japan, Sep. 28-Oct. 1, pp. 491-506. (slides + accepted version)

E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs," Cryptology ePrint Archive: Report 2010/445, first version - Aug. 2010. (report)

K. Gaj, E. Homsirikamol, and M. Rogawski, “Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs,” in LNCS 6225, Cryptographic Hardware and Embedded Systems - CHES 2010, Santa Barbara, CA, USA, Aug. 2010, pp. 264-278. (slides + accepted version)

eSTREAM:

D. Hwang, M. Chaney, S. Karanam, N. Ton, and K. Gaj, "Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates," Proc. State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pp. 151-162, Feb. 2008. (paper + slides)

K. Gaj, G. Southern and R. Bachimanchi, "Comparison of Hardware Performance of Selected Phase 2 eSTREAM Candidates," Proc. SASC 2007: Stream Ciphers Revisited, ECRYPT eSTREAM workshop, Bochum, Germany, Jan. 31-Feb. 1, 2007. (paper + slides)

The eSTREAM Project: Hardware Performance Evaluations

NESSIE

Deliverables of the NESSIE Project

AES

K. Gaj and P. Chodowiec, "Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard using Field Programmable Gate Arrays," LNCS 2020, Progress in Cryptology - CT-RSA 2001, Ed. D. Naccache, RSA Conference 2001 - Cryptographers' Track, San Francisco, Apr. 2001, pp. 84-99. (paper + slides)

K. Gaj and P. Chodowiec, "Hardware performance of the AES finalists - survey and analysis of results," Technical Report, George Mason University, Sep. 2000. (report)

K. Gaj and P. Chodowiec, "Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware," Proc. 3rd Advanced Encryption Standard Conference, New York, April 2000, pp. 40-54. (paper + slides)

K. Gaj and P. Chodowiec, "Implementations of the Twofish Cipher Using FPGA Devices," Technical Report, George Mason University, Jul. 1999. (report)