ATHENA
The most recent alpha version is version 0.6.5.
This version was posted on October 7, 2014, and is available below in two variants:
- For Windows: ATHENa W_0.6.5.2014-10-07
- For Linux: ATHENa L_0.6.5.2014-10-07
The corresponding tutorial (also included in the zip files) is available here:
The History of Changes since ATHENa 0.6 is listed at the end of the Tutorial.
Below we list our development plan from version 0.1 to version 1.0.
0.1 - support for Xilinx FPGAs in a single_run mode;
placement_search - automated search for an optimum placement
starting point (optimum value of a cost table)
0.2 - support for Altera FPGAs
0.3 - exhaustive search for optimum options of synthesis and
implementation tools, enhanced error handling capability
0.4 - new enhanced ATHENa setup, support for multi-core
processing, automated verification of designs through
functional simulation run in batch mode, enhanced progress
reports
0.5 - new heuristic optimization algorithms:
frequency_search and GMU_Xilinx_optimization_1; spooler script
0.6 - support for Linux, new heuristic optimization strategy:
GMU_optimization_1, iteration through multiple values of generics,
new FPGA families (Spartan 6, Virtex 6, Cyclone IV, Stratix IV,
Arria families), support for Verilog and AHDL, support for using
ATHENa with Altera MegaWizard Plug-in Manager and Xilinx CORE
Generator, data trimming mode, database report generator, support
for purely combinational circuits, capability to create
replication files that can be used to regenerate optimized results
without using ATHENa, tutorial converted to LaTeX.
0.7 - automated verification of designs through
post-synthesis and timing simulation in batch mode
0.8 - support for Microsemi (formerly Actel) FPGAs
0.9 - additional heuristic optimization algorithms
1.0 - accommodating comments received by users testing earlier
versions.
We reserve the right to introduce changes to this development
plan.
The timeline of the project will depend on the future availability
of human resources, funds, and contributions by volunteers
interested in co-developing the system.
Current and earlier versions of the environment have been
extensively tested by students taking the following
graduate classes at George Mason University:
Fall 2015:
ECE 545 Digital System Design with VHDL
Fall 2014:
ECE 545 Digital System Design with VHDL
Fall 2012:
ECE 545 Digital System Design with VHDL
Spring 2012:
ECE 645 Computer Arithmetic
Fall 2011:
ECE 545 Digital System Design with VHDL
Spring 2011:
ECE 645 Computer Arithmetic,
ECE 746 Applied Advanced Cryptography
Fall 2010:
ECE 545 Digital System Design with VHDL,
ECE 646 Cryptography and Computer Network Security