Hash Function FPGA Ranking

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    • Round 3 SHA-3 Candidates & SHA-2
    • Round 2 SHA-3 Candidates & SHA-2
    • High Speed Implementations, Single Message Architectures
    • High Speed Implementations, All Architectures
    • Low Area Implementations
    • 256
    • 512
    • No
    • Yes
    • Any
    • Without Embedded Resources (Block Memories, DSP Units, etc.)
    • Without Primitives or Megafunctions
    • Source Available
    • Throughput/Area
    • Throughput
    • Area

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Result ID Algorithm Arch Type Primary Opt Target Hash Size [bits] TP/LEs [(Mbits/s)/LEs] TP/ALUTs [(Mbits/s)/ALUTs] TP/CLB Slices [(Mbits/s)/CLB Slices] TP [Mbits/s] LEs ALUTs CLB Slices BRAMs Memory Bits DSPs Primary Designer Affiliation Primary Designer Name(s) Src Avail Family Padding Max #Streams Group Megafunctions or Primitives