News

This is the archive of news previously and currently shown on our main page. Seminars are posted on the seminar page. Our latest publications are posted on the publications page.

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2011

Dr. Kaps ia a member of the Program Committee of COSADE 2012

Dr. Kaps is a member of the Program Committee of Third International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE) to be held in Darmstadt, Germany on May 3-4, 2012. For more information about the conference please have a look at the Call for Papers. (09/14/11)

Dr. Kaps spoke at FPL 2011

Dr. Kaps gave a presentation entitled "Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs" at the 21st International Conference on Field Programmable Logic and Applications (FPL 2011) held in Chania, Greece, on Sep. 5-7, 2011. (09/14/11)

Dr. Gaj and Dr. Kaps spoke at DSD 2011

Dr. Gaj and Dr. Kaps spoke at the 14th Euromicro Conference on Digital System Design (DSD 2011) that took place in Oulu, Finland, from August 31st to September 2nd, 2011. Dr. Gaj delivered a keynote address, entitled "Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware" (PDF). His keynote was attended also by attendees of the co-located event: 37th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2011). Dr. Kaps gave a presentation entitled "A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs" at the DSD session on "Architectures and Hardware for Security Applications". The GMU paper presented by Dr. Kaps was one of the three DSD 2011 papers nominated for the best paper award. (09/14/11)

Dr. Gaj is a member of the Program Committees of FPT 2011 and CT-RSA 2012

Dr. Gaj is a member of the Program Committees of FPT 2011 (The 2011 International Conference on Field-Programmable Technology) to be held in New Delhi, India, on Dec. 12-14, 2011, and CT-RSA 2012 (The Cryptographers' Track at the RSA Conference 2012). to be held in San Francisco, USA, on Feb. 27-Mar. 2, 2012 (07/21/11).

CERG Announces the Release of ATHENa Version 0.6.2

CERG released version 0.6.2 of the Automated Tool for Hardware EvaluatioN (ATHENa) on 06/16/11. The new features of this version include: capability to create replication files that can be used to regenerate optimized results without using ATHENa, support for source files in AHDL, allowing purely combinational circuits, fixing minor errors related to the use of embedded resources, support for Quartus II 10.1 and Xilinx ISE 12.4 & 13.1, and a new format of the tutorial obtained by converting it to LaTeX. The latest release can be donwloaded from the download section of the ATHENa webpage. (06/16/11)

Quo Vadis 2011 in Warsaw

CERG in collaboration with ENIGMA Information Security Systems Sp. z o.o. organized the 7th International Workshop on the state of the art in cryptology and new challenges ahead, entitled "Quo Vadis Cryptology?" The topic of this year's workshop was the SHA-3 contest. The contest, organized by NIST, aimed at selecting a new cryptographic hash function standard from among 64 initial submissions. The number of competing candidates was first reduced to 14 in July 2009, and then to the final 5 in December 2010. The winner of the contest is scheduled to be announced in the second quarter of 2012.

The workshop opened with the presentation by Bill Burr, the recently retired manager of the NIST Cryptographic Technology Group, who led the competition from its beginning till the end of Round 2 in December 2010. Day 1, entitled Battle of Algorithms, focused on presentations of final candidates by representatives of the design teams, and the initial security analysis. Day 2, entitled, Comprehensive Evaluations, featured talks by experts conducting evaluations and comparisons of the SHA-3 candidates from the point of view of security and efficiency in software (microprocessors and microcontrollers) and hardware (FPGAs and ASICs). (05/24/2011)

Dr. Gaj is a co-chair of the special track at ReConFig 2011

Dr. Gaj and Dr. Viktor Fischer from Université de Saint Etienne, France, are co-chairs of the special track on Reconfigurable Computing for Security and Cryptography at the 2011 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2011, to be held in Cancun, Mexico, on Nov. 30 - Dec. 2, 2011. The submission deadline for this conference is July 22, 2011. (05/15/11)

Dr. Gaj is a member of the Program Committees of CHES 2011 and CSS 2011

Dr. Gaj is a member of the Program Committees of CHES 2011 (Cryptographic Hardware and Embedded Systems workshop) to be held in Nara, Japan on Sep. 28-Oct. 1, 2011, and CSS 2011 (Cryptography and System Security workshop) to be held in Naleczow, Poland, on Sep. 26-28, 2011. (05/15/11)

Dr. Kaps and Dr. Gaj spoke at CryptArchi 2011

Dr. Kaps and Dr. Gaj gave presentations at the 9th International Workshop on Cryptographic Architectures Embedded in Reconfigurable Devices, CryptArchi 2011, in Bochum, Germany, on June 15-18, 2011. The titles of their respective talks are: " Scalability of SHA-3 Finalists for Lightweight Implementations on FPGAs" and " Investigating Design Space of Five Final SHA-3 Candidates in High-Performance FPGAs." (06/03/11)

Dr. Gaj and Marcin Rogawski spoke at Hash 2011

Dr. Gaj and Marcin Rogawski gave two talks at the ECRYPT II Hash Workshop 2011 held in Tallinn, Estonia, on May 19-20, 2011. The GMU talks are entitled respectively "Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architecture in Xilinx and Altera FPGAs," and "Use of Embedded FPGA Resources in Implementations of Five Round Three SHA-3 Candidates." (05/15/11)

Dr. Kaps is a Member of the Program Committee of (AHSA) - Architectures and Hardware for Security Applications 2011

"(AHSA) - Architectures and Hardware for Security Applications" is a special session of the 14^th EUROMICRO Conference on Digital System Design (DSD) which is to be held in Oulu, Finland on August 31st - September 2nd 2011. The focus of this special session is on all aspects of cryptographic and security hardware systems. Of special interest are contributions that describe new methods for secure and efficient hardware implementations for embedded systems, e.g. smart cards, microprocessors, DSPs, RFID and Wireless Sensor Networks, etc. All submitted papers will be reviewed anonymously. The submission deadline is March 14^th. For more information please have a look at the Call for Papers. (01/05/11)

CERG Announces the Release of ATHENa Version 0.6.1

CERG released version 0.6.1 of the Automated Tool for Hardware EvaluatioN (ATHENa) on 12/14/10. This is the first release that runs on Windows as well as on Linux. The other new features of this release are a new comprehensive optimization strategy for Altera and Xilinx FPGAs: GMU_optimization_1, the possibility of iterating through multiple values of generics, support for Verilog files and usage of ATHENa together with Altera MegaWizard Plug-in Manager and Xilinx CORE Generator. In addiditon the latest FPGA families from Xilinx and Altera, namely Spartan 6, Virtex 6, Cyclone IV, Stratix IV, and Arria are now supported. Last but not least a database report generator was added to generate database entries containing selected results to be uploaded to the ATHENa database. The latest release can be donwloaded from the download section of the ATHENa webpage. (01/04/11)