5.2. DUT Control Module

This module controls the operation of the Device Under Test (DUT) and provides the clock signal for the DUT as well as functions that are related to the DUTs clock domain.

5.2.1. Setting DUT Clock

The control board can provide a clock for the DUT ranging from 400 KHz to 100 MHz. The default value is 5 MHz. To set it, use the following method:

ctrl.setDUTClk(clkValue)

Note: Setting the DUT clock will set the OutLen, TriggerMode, DUTInterface back to default settings as well as reset the DUT.

5.2.2. DUT Selection

The target connector (FOBOS Shield) is based on the ChipWhisperer target connector. Some DUTs though do not follow the FOBOS target connector specification. This module allows to switch the pin mappings based on the selected DUT. The DUT options are:

  • DUT_FOBOS : A DUT that follows the FOBOS target connector specification

  • DUT_CW305 : The ChipWhisperer CW305 board does not connect the reset pin to the FPGA. Therefore, we use the FD2C_CLK pin for FC_RST.

  • DUT_MTC : Enables I2C communication to a microcontroller DUT connected to the FOBOS Multi-Target Connector (MTC).

  • DUT_CW308 : Enables serial communication.

ctrl.setDUT(FOBOSCtrl.Value)

5.2.3. Trigger Settings

The controller can send a trigger to the Oscilloscope once the DUT starts processing the data (i.e., di_ready = 0). Or it can be configured to trigger any number of clock cycles after this event occurs.

  • TRIGGER_WAIT_CYCLES : The number of clock cycles after which the trigger is asserted (after di_ready goes to zero).

  • TRIGGER_LENGTH_CYCLES : The time the trigger signal is asserted.

  • TRIGGER_TYPEpossible values: TRG_NORM | TRG_FULL | TRG_NORM_CLK | TRG_FULL_CLK

    • TRG_NORM : normal trigger mode. In this mode the TRIGGER_WAIT_CYCLES and TRIGGER_LENGTH_CYCLES are applied.

    • TRG_FULL : Full trigger mode. While DUT is running (between di_ready = 0 and do_valid = 1) the trigger is asserted.

    • TRG_NORM_CLK : same as TRG_NORM but the trigger signal is AND-ed with the clock.

    • TRG_FULL_CLK : same as TRG_FULL but the trigger signal is AND-ed with the clock.

ctrl.TriggerMode(FOBOSCtrl.Value)

5.2.4. DUT Reset Feature

In some cases, the control board may need to reset the DUT because the interesting part of the victim algorithm has already executed. This is specifically valuable for ciphers that take a long time to complete. In this case, the cipher runs for a configurable number of clock cycles and then is reset without waiting for it to complete. This helps reduce acquisition time. The number of cycles is counted after di_ready goes to 0. Note: When you use this feature, no output is returned from the DUT. To set it use the following command and set TIME_TO_RESET to any number other than zero. This number is set to zero by default which disables this feature.

ctrl.setTimeToReset(TIME_TO_RST)

5.2.5. Timeout Setting

In some cases, due to communication error or DUT non-responsiveness the control board sends a timeout error message to the control PC when a configurable time has elapsed. The default value is 5 seconds which is enough for almost all cases. Once timeout is reached, the control board resets the DUT, clears any pending DUT data transfers and return the timeout status to the capture software. To set the timeout value, use the method:

ctrl.setTimeout(TIMEOUT)

5.2.6. Glitch Setting

5.2.7. DUT Working Counter

This module counts the number of clock cycles that passed between the DUT starting an operation to when it completes the operation. This is very useful for automatic benchmarking and for verifying simulation results.

ctrl.getWorkCount()