4. FOBOS DUT

A DUT (Design Under Test) board must be connected to the control board to run SCA.

4.1. Setup DUT Board

This section describes how to connect the supported DUTs to FOBOS Control and how to modify the DUT Boards if needed. FOBOS supports the following boards as DUT:

• 4.1.1. FOBOS FBD-A7 (Artix7 FPGA)
• 4.1.2. Digilent Nexy3 (Spartan 6 FPGA)
• 4.1.3. NewAE CW305 (Artix7 FPGA)

4.2. FOBOS DUT Interface

This section describes how to interface a cryptographic hardware implementation with FOBOS. As part of FOBOS, we provide a wrapper for implementations that follow a simple AXI stream protocol interface such as the GMU LWC Hardware API interface as described in Section 4.2.4.

• 4.2.1. FOBOS DUT Communication
• 4.2.2. FOBOS Wrapper
• 4.2.3. Crypto Core Interface
• 4.2.4. GMU LWC Hardware API

4.3. Example Algorithm Implementations

This section describes how to compile the provided example AES for use with FOBOS, as well as a GMU LWC Hardware API compatible implementation of ASCON from the Ascon Team, and the dummy DUT that we provide. The dummy DUT is a great starting point for making your own hardware implementation of a cryptographic algorithm compatible with FOBOS.

• 4.3.1. AES Example
• 4.3.2. ASCON Example
• 4.3.3. Dummy DUT Example