Panasayya Yalla

Contact

George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
 Office: Engineering Building, Room 3231
Phone (lab): 703-993-1609
E-Mail: pyalla'at'gmu.edu
PGP Key ID: 0xD9190217

Research Interest

Panasayya's research interests includes computer arithmetic, cryptography for resource constrained devices, differential power analysis attacks and efficient hardware implementations on FPGAs for lightweight applications.

Advisor: Dr. Jens-Peter Kaps

Biography

Panasayya received his Master's degree in Computer Engineering and the Ph.D. degree in Electrical and Computer Engineering from George Mason University in 2009 and 2017, respectively. He earned his Bachelor's degree from Sir C.R.Reddy college on Engineering, Eluru, India in 2006.

Publications

  • P.S.V.V.K. Yalla, Methodology for developing lightweight architectures for FPGAs, ECE Department, George Mason University, Fairfax, Virginia, USA, Dec, 2017, Ph.D. Dissertation [pdf] [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • P. Yalla and J.-P. Kaps, Evaluation of CAESAR hardware API for lightweight implementations, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • W. Diehl, F. Farahmand, P. Yalla, J.-P. Kaps, and K. Gaj, Comparison of hardware and software implementations of selected lightweight block ciphers, 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, Sep., 2017 [Bibtex]
  • P. Yalla, E. Homsirikamol, and J.-P. Kaps, Comparison of multi-purpose cores of Keccak and AES, Design, Automation Test in Europe DATE 2015, ACM, pages 585–588, Mar, 2015 [Bibtex]
  • R. Velegalati and P. Yalla, Differential power analysis attack on FPGA implementation of AES, George Mason University - ECE Department, May, 2008 [pdf] [Bibtex]
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, and S. Gurung, Lightweight implementations of SHA-3 finalists on FPGAs, Mar, 2012 [pdf] [Bibtex]
  • J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, and J. Pham, Lightweight implementations of SHA-3 candidates on FPGAs, Progress in Cryptology – INDOCRYPT 2011, Lecture Notes in Computer Science (LNCS), volume 7107, Springer Berlin / Heidelberg, pages 270–289, Dec, 2011 [pre-print, pdf] [Bibtex]
  • P.S.V.V.K. Yalla, Differential power analysis on light weight implementations of block ciphers, ECE Department, George Mason University, Fairfax, Virginia, USA, July, 2009, Master's Thesis [Bibtex]
  • P. Yalla and J.-P. Kaps, Lightweight cryptography for FPGAs, International Conference on ReConFigurable Computing and FPGAs – ReConFig'09, IEEE, pages 225–230, Dec., 2009 [pre-print, pdf] [Bibtex]
  • P. Yalla and J.-P. Kaps, Compact FPGA implementation of Camellia, Field Programmable Logic and Applications, FPL 2009, IEEE, pages 658–661, Aug., 2009 [pre-print, pdf] [Bibtex]