Malik Umar Sharif

Contact

3100 Engineering Building
George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
 Office: Engineering Building, Room 3231
Phone (lab): 703-993-1561
E-Mail: msharif2'at'gmu.edu

Research Interests

  • Hardware Implementations of Cryptographic Algorithms
  • Computer Arithmetic
  • Reconfigurable Computing
  • Embedded Systems
  • Microprocessor System Development

Advisor: Dr. Kris Gaj

Biography

Umar graduated from George Mason University with the Ph.D. degree in Electrical and Computer Engineering in Summer 2017. He received his M.S. degree in Computer Engineering from GWU in 2009.

Publications

  • F. Farahmand, M.U. Sharif, K. Briggs, and K. Gaj, A high-speed constant-time hardware implementation of NTRUEncrypt SVES, International Conference on Field Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December, 2018 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Hardware-software codesign of RSA for optimal performance vs flexibility trade-off, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, Aug. 29-Sep. 2, 2016 [Bibtex]
  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Jun., 2012 [Bibtex]
  • K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, and M.U. Sharif, Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs, Mar, 2012 [Bibtex]
  • R. Shahid, M.U. Sharif, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of 14 Round 2 SHA-3 candidates, The 2011 International Conference on Field-Programmable Technology, FPT 2011, Dec., 2011 [Bibtex]
  • M.U. Sharif, R. Shahid, M. Rogawski, and K. Gaj, Use of embedded FPGA resources in implementations of five round three SHA-3 candidates, May, 2011, ECRYPT II Hash Workshop 2011 [Bibtex]