Ahmed Ferozpuri

Contact

3100 Engineering Building
George Mason University
ECE Department, CERG
4400 University Drive, MS 1G5
Fairfax, VA 22030
 Office: Engineering Building, Room 3231
Phone (lab): 703-993-1609
E-Mail: aferozpu'at'gmu.edu
Personal Homepage: aqf-ite.com

Research Interests

  • Design and Verification of FPGA-based embedded systems
  • Post-quantum cryptography
  • Physical Unclonable Functions
  • Machine Learning
  • Neural Networks
  • Blockchains
  • Trusted Execution

Other Interests

  • High Level Synthesis
  • Hardware Software Codesign
  • Virtualization
  • Heterogeneous computing
  • New computing architectures
  • Quantum Computing

Advisor: Dr. Kris Gaj

Biography

Ahmed Ferozpuri graduated Cum Laude from George Mason University in 2007 with a B.S. in Electrical Engineering and a B.S. in Computer Science. After graduating, Ahmed worked for various DoD contractors in Northern Virginia specializing in cell-phone based electronics, network analysis, and radar systems. He gained experience developing and designing embedded systems, high-level C++ programs for network analysis, and Java programs for data visualization. As an independent contractor, Ahmed has developed professional websites and programs using CSS/HTML, PHP, MySQL, Javascript, Flash, and various content management systems.

In Fall 2014 - Fall 2017, Ahmed worked on his M.S. degree in Computer Engineering specializing in cryptography and digital design. During this time he has worked on the following projects;

  • High-speed Hardware implementation of several candidates from the Competiation for Auenticated Encryption: Security, Applicability, and Robustness (CAESAR)
  • Efficient design, implementation and testing of Physical Unclonable Functions (PUFs) on FPGAs
  • Using Machine Learning to attack PUFs
  • Using FPGAs to secure off-chain computation via Trusted Execution Environments

In Fall of 2017 he defended his Master's thesis.

Publications

  • F. Farahmand, D.T. Nguyen, V.B. Dang, A. Ferozpuri, and K. Gaj, Software/hardware codesign of the post quantum cryptography algorithm NTRUEncrypt using high-level synthesis and register-transfer level design methodologies, 29th International Confererence on Field-Programmable Logic and Applications, FPL 2019, Barcelona, Spain, Sep., 2019 [Bibtex]
  • A. Ferozpuri and K. Gaj, High-speed FPGA implementation of the NIST Round 1 Rainbow signature scheme, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December, 2018 [Bibtex]
  • F. Farahmand, A. Ferozpuri, W. Diehl, and K. Gaj, Minerva: Automated hardware optimization tool, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, IEEE, Dec., 2017 [Bibtex]
  • A. Salman, A. Ferozpuri, E. Homsirikamol, P. Yalla, J.-P. Kaps, and K. Gaj, A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2017), Cancun, Mexico, Dec, 2017 [Bibtex]
  • E. Homsirikamol, W. Diehl, A. Ferozpuri, F. Farahmand, M.U. Sharif, and K. Gaj, A universal hardware API for authenticated ciphers, Proc. 2015 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2015, IEEE, Dec, 2015 [Bibtex]